https://tube.ekaii.fr/videos/watch/6232c918-34ca-41f4-b95e-abfa15714aa8 The 1.0 RISC-V Vector Specification is now Ratified, and the first pieces of silicon using the new spec are starting to hit the shelves. I go over the utility of Vector Instructions, why you would want them, why you should care, and how to use them in raw assembly code! We also touch on some complex computer engineering topics like Vector Length Agnosticism. By the end of this video, you'll understand why this is such an exciting time in computing history! Note: This video is not sponsored, I just think the K230 is an interesting chip. RISC-V Official 1.0 Vector Spec: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 Follow LaurieWired on Social Media: ►https://linktr.ee/lauriewired Timestamps: 0:00 RISC-V ISA Overview 1:50 What are Vector Instructions? 5:46 0.7 Draft Spec vs 1.0 Ratified Spec 7:13 SoC Overview 8:15 Vector Assembly Code 11:01 Real Time Demonstration + GDB 13:20 FFmpeg RISC-V Vector Patch 14:51 Closing Thoughts — mirrored from https://www.youtube.com/watch?v=Ozj_xU0rSyY Sun, 21 Jun 2026 21:19:16 GMT https://validator.w3.org/feed/docs/rss2.html PeerTube - https://tube.ekaii.fr https://tube.ekaii.fr/client/assets/images/icons/icon-1500x1500.png https://tube.ekaii.fr/videos/watch/6232c918-34ca-41f4-b95e-abfa15714aa8 All rights reserved, unless otherwise specified in the terms specified at https://tube.ekaii.fr/about and potential licenses granted by each content's rightholder.